Scalable high speed packet switch using packet diversion through dedicated channels

ABSTRACT

A scalable high-speed packet switching device includes a packet switch with ports, a crosspoint matrix, and a plurality of subswitches, one for each port of the packet switch. A processor in the packet switch detects a high level of traffic between two ports and causes the subswitches and crosspoint matrix to divert packets away from the packet switch and through a dedicated channel in the crosspoint matrix.

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates generally to packet switching devices, and moreparticularly to a packet switch which can be scaled up to handle a largenumber of ports without a corresponding decrease in performance. Theinvention provides a technique for detecting high traffic levels betweentwo ports and diverting packets between such ports through a dedicatedchannel.

2. Related Information

Packet switching techniques are conventionally used to transmit varioustypes of digital data such as digitized voice, computer data, and videosignals. Data (e.g., a telephone voice signal) is broken up into packetseach of a specified size, wherein each packet typically includes, inaddition to the digital data, a header indicating a destination addressto which the packet should be sent. A packet switching network made upof packet switches can be used to route packets to their respectivedestinations without delay. See, for example, U.S. Pat. No. 5,544,160 toCloonan et al., entitled "Terabit per Second Packet Switch".

Packet switches may also be used in smaller communication networks toroute data between devices. As one example, an interofficevideoconferencing system may have a requirement to selectively transmitdigitized video and audio information to one or more recipients througha centralized switch. A packet switch can be designed to handle suchdigitized information, so that packets comprising a video signal fromone video conference participant are switched to all participants of thevideo conference.

As the size of packet switching networks has grown, the complexity andprocessing requirements of packet switching devices has increased. Forexample, the number of ports required for a particular packet switch hasincreased, requiring faster processors to handle the increased traffic.

Conventional packet switches (i.e., devices which route packets ofdigital data between two sets of ports) are well known. FIG. 1 shows insimplified form a conventional packet switch architecture including aCPU 101, a routing table 102, buffer memory 103, data bus 104, andpacket interfaces 105 through 111 each corresponding to a port. Packetsarrive at a port (e.g., port 1) and are routed to a destination port(e.g., port 2) based on information contained in packet headers.

Most packet switches rely on fast software to route packets. As shown inFIG. 1, for example, incoming packets are received by packet interfaces105 through 111 and interpreted by CPU 101. CPU 101 temporarily storesincoming packets into buffer memory 103 and examines each packet headerto determine which port the packet should be routed to for output. Thisexamination usually involves searching a look-up table of addressesversus ports stored in routing table 102. The table includes a list ofaddresses and ports which are most advantageous to route the packet fora given address. Following the look-up operation, the packet is placedin the correct packet interface and sent to the destination port.Special messages can be transmitted to the packet switch to changerouting table 102, thus changing the network routing parameters.

One problem with the conventional architecture of FIG. 1 is that it cantake a long time to sort through routing table 102. As a network grows,the number of potential distant packet addresses grows. In fact, it maybe that the packet routing table can be billions of addresses long,severely bogging down CPU 101.

The time it takes to receive and store packets while the routing processis underway will limit the number of ports that a packet switch cansupport. It also limits the number of packets that can be routed persecond. A given CPU has a finite processor bandwidth Z. This bandwidthwill allow the CPU to successfully route X packets per second. Eachpacket interface has a bandwidth or maximum packet speed Y in packetsper second. Thus, the number of ports N that can be successfullyserviced by this type of packet switch is limited to N(max)=X/Y.

A packet switch based on the architecture of FIG. 1 can only be scaledas far as the CPU bandwidth is scaled. This is difficult, as there is alimit on the processing bandwidth of a single CPU. Consequently, packetswitches based on the general architecture shown in FIG. 1 cannot beeasily scaled to support a large number of ports or addresses.

SUMMARY OF THE INVENTION

The present invention overcomes the aforementioned problems by providinga scalable packet switch which can be though of as a hybrid between a"connectionless" switch and a "connectioned" switch. The architecturecan scale to a much larger number of ports, and is not limited by thebandwidth of a single CPU. The scalable packet switch, in response todetecting a high traffic rate between two node addresses (and hencebetween switch ports), creates a dedicated path between the ports forpackets between those nodes, thus diverting the packets away from abottleneck in the switch.

In one embodiment, the packet switch includes a conventional packetswitch which is augmented with an additional subswitch per port and acrosspoint matrix. Each subswitch is designed to switch packets to oneof only two possible destinations: the conventional packet switch or tothe crosspoint matrix. By limiting each subswitch to only three ports,the processor bandwidth can be fully used, thus allowing the packet persecond rate per port to be absolutely maximize.

The new scalable switch takes advantage of a well-known property ofpacket communications: the majority of the packets sent through a switchare sent as part of a stream of packets. In other words, an applicationusing packet transmission will usually engage in a session with anotherlocation served by a particular port. This session will continue forsome time, with most of the traffic being transmitted between the twodistant ends. When the session is over, the two parties will then moveon to other sessions, between other distant parties. During eachsession, however, there is little packet traffic that is not transmittedbetween the two parties and thus between two particular ports.

In accordance with the invention, a dedicated connection is provided totransmit certain packets directly between ports (avoiding the mainpacket switch) while still allowing other packets to travel through themain packet switch.

Additional features and advantages of the present invention will becomeapparent through the following detailed description, the figures, andthe appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a conventional packet switch architecture which uses a CPUto look up address/port entries in a routing table.

FIG. 2 shows a packet switch in accordance with one embodiment of thepresent invention, including a crosspoint matrix 201, a plurality ofpacket subswitches 203 through 205 and a main packet switch 202.

FIG. 3 shows one embodiment of a packet subswitch of the type used inthe system of FIG. 2.

FIG. 4 shows a video conferencing system employing a high speed packetswitch to route video and audio packets among conference participants.

FIG. 5 shows a method for dynamically reconfiguring a crosspoint matrixto provide a dedicated path between high-traffic ports.

FIG. 6 shows a method for routing packets at each subswitch.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows a packet switch which employs various principles of thepresent invention. Packet switch 200 includes a conventional packetswitch 202 which is augmented with a crosspoint matrix 201 and anadditional subswitch (203 through 205) per port. In contrast to FIG. 1,where switch ports are arranged across the top of the figure, switchports in FIG. 2 are arranged down the middle of the figure.

In the inventive architecture of FIG. 2, each sub-switch is designed toswitch packets with only two possible destinations. A packet arriving ata port (e.g., PORT 1) can either be routed to the main packet switch 202or to crosspoint matrix 201. In accordance with the invention, packetsflowing between high-traffic ports are diverted through crosspointmatrix 201 using a dedicated path instead of going through packet switch200. Each sub-switch 203 through 205 may comprise a small standardpacket switch with N=3 ports. The operation of FIG. 2 is explained inmore detail below.

FIG. 3 shows one possible embodiment for subswitch 203 of FIG. 2. Bylimiting each subswitch to exactly three ports, the processor bandwidthcan be fully utilized, thus allowing the packet per second rate per portto be absolutely maxims As shown in FIG. 3, each subswitch includes aprocessor such as a CPU 301, a subswitch routing table 302, a buffermemory 303, data bus 304, and three port interfaces 305 through 307. Afirst port interface 305 provides the external packet switch portconnection (i.e., this replaces port interface 105 of FIG. 1). A secondport interface 306 couples the CPU to the cross point matrix. A thirdport interface 307 couples the CPU to the main packet switch (i.e.,packet switch 202 of FIG. 2).

Subswitch routing table 302 and buffer memory 303 may reside indifferent areas within a single computer memory. CPU 301 may compriseany of various commercially available processors, such as 8-bit or16-bit processors. Alternatively, CPU 301 may comprise a portion of anapplication-specific integrated circuit, or may be constructed of otherwell known logic functional units. The essential function of CPU 301 isto route packets between PORT 1 and the crosspoint matrix or the mainpacket switch based on a configuration command.

Normally, subswitch 203 merely transfers incoming packets from PORT 1(through interface 305) to main packet switch 202 (through interface307) and vice versa. However, subswitch 203 can be commanded to createan entry in subswitch routing table 302 such that all packets destinedfor a particular address are instead diverted to crosspoint matrix 201(via port interface 306) and vice versa. Commands to reconfiguresubswitch 203 may be provided either through crosspoint matrix 201 orfrom packet switch 202 via port interface 307. The subswitch may becommanded to divert packets destined for a particular logical address,physical address, node address, port, or any other designation.

The inventive packet switch relies on the fact that when an applicationsuch as video conferencing transmits information between 2 locations, asession is created, causing a large number of packets to flow during thesession. This session will continue for some time, with most of thetraffic being transmitted between the two distant ends. When the sessionis over, the two parties will then move on to other sessions, betweenother distant parties. During the session, there is very little packettraffic that is not transmitted between the two parties.

One example of such a session is a multimedia communications session. Ifa user is sending a series of video or graphics images, then the datawill exhibit a high packet volume directed at the distant end withlittle or no packets sent anywhere else. During this session, a"virtual" connection is established between the two parties.

FIG. 4 shows a videoconferencing system using a high speed packet switchaccording to various aspects of the invention. High speed packet switch450 includes six ports each of which is coupled through appropriatedigital conversion hardware (e.g., A/Ds and D/As 457 through 462) tovideo conferencing stations 451, 452 and 453. Such connections may bemade over a LAN, telephone wires, or other suitable media. High speedpacket switch 450 also includes a traffic rate comparator 450a which maybe implemented in hardware, software, or a combination of the two. Inone embodiment, traffic rate comparator compares traffic levels betweenaddresses flowing through the switch, determines whether a threshold hasbeen exceeded, and causes packets to be diverted through a crosspointmatrix when traffic levels are exceeded between two ports correspondingto the high-traffic addresses.

Each video conferencing station may comprise a personal computer with acolor display, audio equipment including a microphone and speakers, anda video camera such as camera 454. It will be appreciated that othercomponents may also be included in such a video conferencing system toprovide various features such as camera control, filtering, conferencebridging/mixing, etc.

Video and audio information from each conference station is digitizedand transmitted to high speed packet switch 450, which is constructed inaccordance with the architecture of FIGS. 2 and 3. Packet switch 450examines each incoming packet and routes the packet to its destinationport. For example, if conference station 453 is conducting a videoteleconference with conference station 451, packet switch 450 routesdata packets containing video and audio information from station 453(received on port 1) to station 451 (through port 6). Similarly, packetswitch 450 routes data packets containing video and audio informationfrom station 451 (received on port 5) to station 453 (through port 2).It will be appreciated that bi-directional ports may be used instead ofunidirectional ports.

In contrast to conventional systems, however, packet switch 450 detectsthe condition that a large traffic volume is flowing between therespective ports, and reconfigures subswitches within the packet switchto transmit data through the crosspoint matrix rather than looking upeach address in the main packet switch. Accordingly, increased trafficvolume can be handled.

Referring again to FIG. 2, processing requirements on the main packetswitch 202 are greatly reduced by diverting packets destined for aparticular port through crosspoint matrix 201. Crosspoint matrix 201,which may comprise a digital crosspoint matrix, can establish a directlink between two of the sub-switch ports in the overall switch. Thismatrix can be controlled by the CPU in main packet switch 202 over acontrol line CONTROL. When main packet switch 202 detects a high trafficrate between two ports, it controls crosspoint matrix 201 to establish adirect connection between the appropriate subswitches. Main switch 202informs, through special control packets or via direct control signals,the subswitches to route the connected traffic for those addressesdirectly through the crosspoint direct connection instead of throughmain switch 202. In the case where data is not part of the "virtualcircuit", it is directed to the main packet switch and routed in thenormal manner.

Crosspoint matrix 201 may comprise any of various types of crosspointswitches which provide a dedicated path between two designated ports.Such crosspoint switches are well known an no further elaboration isneeded. Packet switch 202 may comprise any of various types of packetswitches which route incoming packets to one or more destination portsbased on address information in a packet header (e.g., see FIG. 1). Incontrast to conventional packet switches, however, packet switch 202 mayinclude a CPU which detects a condition that a large number of packetsare flowing between two addresses (or ports) and generates a signal oncontrol line CONTROL to configure crosspoint matrix 201 to providededicated paths between two corresponding subswitches. Additionally, thecorresponding subswitches are commanded to divert incoming and outgoingpackets for the particular addresses through crosspoint matrix 201rather than through packet switch 200. Each subswitch can accomplishthis function by creating an entry in its corresponding subswitchrouting table to reflect new port assignments.

Diverting traffic through crosspoint matrix 201 offloads main packetswitch 202 from making repetitive packet routing. In some systems, suchas multi-media communications systems, 90% or more of the packet trafficwould be associated with these virtual connections. In this case thecrosspoint matrix acts as a high-speed accelerator. In many systems ofthis kind the connection-oriented packet traffic is 99.99% or more ofthe total.

FIG. 5 shows a method for detecting traffic patterns and reconfiguringthe packet switch according to one aspect of the present invention. Themethod may be implemented, for example, in a conventional packet switchby reprogramming the CPU to monitor traffic and issue commandsaccordingly. Alternatively, separate circuitry can be provided to detecttraffic patterns and configure the crosspoint matrix and portsubswitches. It may also be possible to implement the traffic monitoringfunction directly in the subswitches, such that the subswitchesthemselves detect traffic patterns and issue commands to reconfigure thecrosspoint matrix and subswitch routing tables. All of thesepossibilities are well within the scope of the present invention.

Beginning with step 501, the traffic level between pairs of addresses orports is monitored. This may be accomplished in any of various ways,such as creating an entry for each pair of source/destination addressesand incrementing a packet counter for each packet which passes throughthe pair corresponding to the entry. Once the address has beenestablished, a port number can be established or determined.

In step 502, a test is made to determine whether the traffic levelbetween the two ports exceeds a threshold. The threshold may bestatically created or may be dynamically reconfigured depending on thecircumstances (i.e., select the highest 10 traffic ports; select allports which exceed a predetermined limit; or use statistical samplingtechniques). If the threshold has not been exceeded, the monitoringcontinues in step 501.

If a traffic threshold has been exceeded, then in step 503 thecrosspoint matrix is reconfigured to create a dedicated path between thetwo ports for the specified addresses. Additionally, in step 504, thesubswitches associated with each port are commanded to divert trafficfor the specified address. In one embodiment, when traffic levels fallbelow a specified minimum, the diversion of packets may be reversed.

Suppose that three nodes in a system are communicating (nodes 1, 2, and3). Assume that nodes 1 and 2 are conducting a video conference or othermultimedia session which involves a large quantity of traffic, and node3 only periodically transmits a message to the other two nodes. Inaccordance with one aspect of the invention, a large traffic volumebetween nodes 1 and 2 would be detected, and a dedicated path would beestablished for communicating between ports for those nodes bycommanding two subswitches corresponding to the ports to divert packetsgoing to or coming and the specified nodes through the crosspointmatrix. However, packets going to or coming from node 3 would not bediverted through the crosspoint matrix, and would instead travel throughthe packet switch according to conventional packet switching techniques.

FIG. 6 shows a method for routing packets at each subswitch. Beginningin step 601, each subswitch processor looks up an address extracted froman incoming packet header in the local subswitch routing table. In step602, if a tag associated with that address indicates that the packetshould be routed to the crosspoint matrix, then in step 603 the packetis routed to the crosspoint matrix and hence directly to anothersubswitch. If, on the other hand, the tag or port assignment indicatesthat the packet should not be routed to the crosspoint matrix, then instep 604 the subswitch routes the packet to the main packet switch whereit is processed normally.

A switch constructed in accordance with the inventive principles isscalable since each sub-switch is associated with a port (i.e., N portsrequires N sub-switches). The crosspoint matrix also grows with thenumber of ports and can be implemented in digital hardware. Although itscales in complexity as N2, it is feasible to build large crosspointmatrix devices of 100×100 in a single integrated circuit.

There is no speed penalty in the sub-switch as the number of portsincreases. For virtual circuit data the latency through an inputsubswitch, to the output port subswitch, is the same for a small numberof ports as well as for a large number of ports. In cases where the mainpacket switch is off-loaded by 90% the size of the over-all switch cannow grow by a factor of ten because the main packet switch has one tenththe traffic it had before. If the connection oriented traffic is 99% ofthe total, then the scalable switch can grow to one hundred times thesize of a standard packet switch, etc.

The result of implementing a packet switch in accordance with thepresent invention is that with the same CPU type a switch can beimplemented that has many more connection ports. It can scale, dependingon the percentage of traffic that is connection-oriented, to ten or evenone hundred or more times the number of ports on a standard switch.

Another advantage of the scalable switch design is that it reduces theaverage latency through the switch. At first this would not be the case,since for a single isolated packet the route through the scalable switchwould have to go through three switches, the main switch and twosub-switches. However, for connection oriented packets the latency delayin the main switch can very large, depending on the search algorithm.With the scalable switch the latency is limited to the latency of twosub-switches. In addition, the two subswitches have only to make asimple two-way routing decision. In fact, the subswitch, on the inputside, need only route packets by comparing them to a single destinationaddress. That address is the distant destination in the virtualconnection. All other packets go to the main switch.

The one-address routing scheme lends itself to a common speed-uptechnique called "cut-through" addressing. With cut-through routing, thesubswitch looks for the address field as the packet is being receivedand begins transmitting the packet to the proper port even before thewhole packet is received. Because only one address is searched for, itis possible to build a very efficient cut-through switch. This minimizesthe total latency even further.

Finally, on the output sub-switch, the output packet from the mainswitch or from the cross-point matrix is always routed to the outputport. These packets are assumed to be targeted for the distantconnection. In this case, the outbound packet can be very quicklyrouted, using an almost zero latency cut-through technique. The onlyreason for buffering the outbound packet is to prevent a collision fromthe other outbound route. For example, if a packet is arriving to theoutput subswitch from the crosspoint matrix at the same time as a packetfrom the main switch, then the second packet must be buffered while thefirst packet is forwarded.

The advantages of the scalable switch are many. First, the number ofswitch ports possible with a given CPU bandwidth is greatly increased.Conversely, the data rate for each port in the switch can besignificantly increased. Finally, the latency in the switch, on average,can be significantly reduced for the connection-oriented traffic.

It is apparent that many modifications and variations of the presentinvention are possible, and references to specific values are by exampleonly. Switch ports, for example, can be either unidirectional or bidirectional. Various functions can be implemented in either hardware orsoftware or a combination of both.

Reference numerals in the appended method claims identifying steps arefor convenience only and are not intended to imply a necessary orderingof the steps. It is apparent that the method steps of the invention maybe practiced in a different ordered sequence from that illustratedwithout departing from the scope of the invention. It is, therefore, tobe understood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

What is claimed is:
 1. An improved packet switching device, comprising:apacket switch comprising a plurality of switch ports, wherein the packetswitch receives packets at one of the plurality of switch ports,determines a destination switch port for each packet by comparing anaddress in each packet with packet switch routing information, androutes each packet to the destination switch port; a crosspoint matrixcomprising a plurality of matrix ports, wherein the crosspoint matrix isconfigurable to provide direct paths between any two of the matrixports; and a plurality of subswitches, each coupled to the packet switchand to the crosspoint matrix; wherein each subswitch is configurable todivert certain packets away from the packet switch to the crosspointmatrix and to allow other packets to pass through to the packet switch.2. The improved packet switching device of claim 1, wherein eachsubswitch comprises a first subswitch port at which packets are receivedor transmitted; a second subswitch port coupled to the crosspointmatrix; a third subswitch port coupled to one of the plurality of switchports of the packet switch; a processor and a subswitch routing table;and wherein the processor compares an address of each packet arriving atthe subswitch with subswitch routing information stored in the subswitchrouting table and routes packets having an address corresponding to thecrosspoint matrix to the crosspoint matrix and routes packets having anaddress corresponding to the packet switch to the packet switch.
 3. Theimproved packet switching device of claim 2, wherein the processor isresponsive to a subswitch configuration command to change the subswitchrouting information stored in the subswitch routing table.
 4. Theimproved packet switching device of claim 3, wherein the processorreceives the subswitch configuration command from the packet switch inresponse to a traffic rate comparison between two of the plurality ofpacket switch ports.
 5. The improved packet switching device of claim 3,wherein the processor receives the subswitch configuration command fromthe crosspoint matrix.
 6. The improved packet switching device of claim1, wherein each of the switch ports of the packet switch are bidirectional.
 7. The improved packet switching device of claim 1, whereinthe packet switch performs a traffic rate comparison for addressesextracted from packet headers received at the packet switch, and,responsive to determining that a traffic rate between two addressesexceeds a threshold, transmitting a configuration command to two of theplurality of subswitches each corresponding to one of the packet switchports which exhibits the traffic rate which exceeds the threshold todivert subsequent packets containing the two addresses through thecrosspoint matrix.
 8. The improved packet switching device of claim 7,wherein the packet switch further issues a command to the crosspointmatrix to set up a dedicated path between two of the plurality ofsubswitches.
 9. The improved packet switching device of claim 1, whereinthe packets contain packetized video and audio information correspondingto a video teleconference.
 10. A system including the improved packetswitching device of claim 2 and a plurality of video conference stationseach of which transmits and receives packetized video information for aconference participant, wherein each conference station is coupled to atleast one of the first subswitch ports, and wherein during a videoconference between two of the video conference stations, the improvedpacket switching device detects a high traffic rate between the twovideo conference stations and causes subsequent packets between the twovideo conference stations to be diverted through the crosspoint switch.11. An improved packet switching device, comprising:a packet switchcomprising a plurality of switch ports each including a port interfacefor transmitting and receiving packets, a packet switch memory includingrouting information which associates packet addresses with switch ports,and a processor which extracts packet addresses from packets received atthe switch ports, looks up each packet address in the packet switchmemory, determines a destination switch port for each packet address onthe basis of the looked up packet address, and transmits each packetreceived at the switch ports to a respective destination switch port; acrosspoint matrix including a plurality of matrix ports, wherein thecrosspoint matrix is configurable to provide direct paths between anytwo of the matrix ports; and a plurality of subswitches, each subswitchcomprising a first port at which packets are received or transmitted, asecond subswitch port coupled to one of the plurality of matrix ports ofthe crosspoint matrix, a third subswitch port coupled to one of theplurality of switch ports of the packet switch, a subswitch routingmemory which associates packet addresses with either the secondsubswitch port or the third subswitch port, and a processor whichextracts addresses from packets received at the first subswitch port,compares the extracted addresses received from the first subswitch portwith packet addresses in the subswitch routing memory, and transmitspackets received from the first subswitch port to the second subswitchport for packets having extracted addresses associated with the secondsubswitch port in the subswitch routing memory and transmits packetsreceived from the first subswitch port to the third subswitch port forpackets having extracted addresses associated with the third subswitchport in the subswitch routing memory.
 12. The improved switching deviceof claim 11, wherein the packet switch identifies high traffic levelsbetween two of the packet switch ports and, in response thereto, causesthe crosspoint matrix to provide a dedicated path between two of theplurality of subswitches and causes the two subswitches to divertsubsequent packets away from the packet switch and through the dedicatedpath in the crosspoint matrix.
 13. The improved switching device ofclaim 12, wherein the packet switch compares a traffic rate between twopacket addresses extracted from packets flowing between two of theplurality of switch ports with a threshold.
 14. The improved switchingdevice of claim 11, further comprising a traffic comparator circuitwhich, in response to determining that a high traffic rate existsbetween two of the packet switch ports, configures the crosspoint matrixto provide a dedicated path between two of the plurality of subswitches.15. The improved switching device of claim 14, wherein the trafficcomparator circuit configures the two subswitches to divert packetshaving an address corresponding to the high traffic rate through thededicated path of the crosspoint matrix.
 16. A method of improvingperformance in a packet switching device having a plurality of deviceports through which packets are switched, the method comprising thesteps of:(1) detecting a condition that a high traffic rate existsbetween two of the plurality of device ports and through a packet switchcoupled to the device ports; (2) in response to detecting the hightraffic rate, providing a dedicated path which diverts packets havingaddresses associated with the high traffic rate away from the packetswitch, wherein such packets are routed to their destination through thededicated path instead of through the packet switch; and (3) continuingto route packets which do not have addresses associated with the hightraffic rate through the plurality of device ports and the packetswitch.
 17. The method of claim 16, wherein step (2) comprises the stepof configuring a crosspoint matrix, and two subswitches coupled betweenthe crosspoint matrix and to two of the device ports, to divert packetsthrough the subswitches to the crosspoint matrix.
 18. The method ofclaim 17, wherein step (2) comprises the step of using a processor and asubswitch routing table in each of the two subswitches to divert thepackets.
 19. The method of claim 18, wherein step (2) comprises the stepof diverting packets containing digitized audio and video informationassociated with a video teleconference.
 20. The method of claim 18,wherein step (1) comprises the step of using a traffic comparisoncircuit within the packet switch to detect the high traffic rate, andwherein step (2) comprises the step of issuing a command from the packetswitch to a crosspoint matrix to provide the dedicated path.
 21. In apacket switching device having a plurality of ports at which packetshaving routing address information are received and transmitted and apacket switching circuit that routes packets between ports, a method ofimproving performance comprising the steps of:(1) using the packetswitching circuit to route packets between a port where a packet isreceived and at least one other port according to the routing addressinformation; (2) detecting a condition that a high traffic rate existsfor the particular routing address information in step (1); and (3) inresponse to detecting the high traffic rate in step (2), providing adedicated path for subsequent packets having the particular routingaddress information, wherein the dedicated path avoids use of the packetswitching circuit to route subsequent packets.
 22. The method of claim21, wherein step (2) comprises the step of using a traffic ratecomparison circuit within the packet switching circuit to detect hightraffic rates.
 23. The method of claim 21, wherein step (3) comprisesthe step of configuring a crosspoint matrix, and two subswitches coupledbetween the crosspoint matrix and two of the ports, to divert packetsthrough the subswitches to the crosspoint matrix.
 24. The method ofclaim 23, wherein step (3) further comprises the step of using aprocessor and a subswitch routing table in each of the two subswitchesto divert the packets.